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1 features description applications ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 www.ti.com 24-bit analog-to-digital converter for bridge sensors 2 complete front-end for bridge sensors the ads1232 and ads1234 are precision 24-bit analog-to-digital converters (adcs). with an onboard, up to 23.5 effective bits low-noise programmable gain amplifier (pga), onboard, low-noise pga precision delta-sigma adc and internal oscillator, the rms noise: ads1232/4 provide a complete front-end solution for 17nv at 10sps (pga = 128) bridge sensor applications including weigh scales, 44nv at 80sps (pga = 128) strain gauges and pressure sensors. 19.2-bit noise-free resolution at gain = 64 the input multiplexer accepts either two (ads1232) over 100db simultaneous 50hz and 60hz or four (ads1234) differential inputs. the ads1232 also includes an onboard temperature sensor to rejection monitor ambient temperature. the onboard, low-noise flexible clocking: pga has a selectable gain of 1, 2, 64, or 128 low-drift onboard oscillator ( 3%) supporting a full-scale differential input of 2.5v, optional external crystal 1.25v, 39mv, or 19.5mv. the delta-sigma adc selectable gains of 1, 2, 64, and 128 has 23.5-bit effective resolution and is comprised of a 3rd-order modulator and 4th-order digital filter. two easy ratiometric measurements ? data rates are supported: 10sps (with both 50hz and external voltage reference up to 5v 60hz rejection) and 80sps. the ads1232/4 can be selectable 10sps or 80sps data rates clocked externally using an oscillator or a crystal. two-channel differential input with built-in there is also an internal oscillator available that temperature sensor (ads1232) requires no external components. offset calibration is performed on-demand and the ads1232/4 can be four-channel differential input (ads1234) put in a low-power standby mode or shut off simple serial digital interface completely in power-down mode. all of the features of supply range: 2.7v to 5.3v the ads1232/4 are operated through simple pin-driven control. there are no digital registers to ? 40 c to +105 c temperature range program in order to simplify software development. data are output over an easily-isolated serial interface that connects directly to the msp430 and weigh scales other microcontrollers. strain gauges the ads1232 is available in a tssop-24 package pressure sensors and the ads1234 is in a tssop-28. both are fully industrial process control specified from -40 c to +105 c. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2005 ? 2008, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. input mux ds adc refp refn pga gain =1, 2, 64, or 128 cap dvdd dgnd agnd a1/temp (1) a0 note: (1) a1 for ads1234, temp for ads1232. ainp1 ainn1 ainp2 ainn2 ainp3 ainn3 ainp4 ainn4 ads1234only sclk speed drdy/dout pdwn gain [1:0] avdd cap external oscillator internal oscillator clkin/xtal1 xtal2
ordering information absolute maximum ratings ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. for the most current package and ordering information, see the package option addendum at the end of this data sheet, or see the ti website at www.ti.com . over operating free-air temperature range (unless otherwise noted) (1) ads1232, ads1234 unit avdd to agnd ? 0.3 to +6 v dvdd to dgnd ? 0.3 to +6 v agnd to dgnd ? 0.3 to +0.3 v input current 100, momentary ma input current 10, continuous ma analog input voltage to agnd ? 0.3 to avdd + 0.3 v digital input voltage to dgnd ? 0.3 to dvdd + 0.3 v maximum junction temperature +150 c operating temperature range ? 40 to +105 c storage temperature range ? 60 to +150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 www.ti.com
electrical characteristics ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 all specifications at t a = ? 40 c to +105 c, avdd = dvdd = vrefp = +5v, and vrefn = agnd, unless otherwise noted. ads1232, ads1234 parameter conditions min typ max unit analog inputs full-scale input voltage 0.5v ref /gain v (ainp ? ainn) ainxp or ainxn with respect to gnd, agnd ? 0.1 avdd + 0.1 v gain = 1, 2 common-mode input range gain = 64, 128 agnd + 1.5v avdd ? 1.5v v gain = 1 3 na differential input current gain = 2 6 na gain = 64, 128 3.5 na system performance resolution no missing codes 24 bits internal oscillator, speed = high 78 80 82.4 sps internal oscillator, speed = low 9.75 10 10.3 sps data rate external oscillator, speed = high f clk /61,440 sps external oscillator, speed = low f clk /491,520 sps digital filter settling time full settling 4 conversions differential input, end-point fit 0.0002 0.001 % of fsr (1) gain = 1, 2 integral nonlinearity (inl) differential input, end-point fit 0.0004 % of fsr gain = 64, 128 gain = 1 0.2 5 ppm of fs input offset error (2) gain = 128 0.02 1 ppm of fs gain = 1 0.3 v/ c input offset drift gain = 128 10 nv/ c gain = 1 0.001 0.02 % gain error (3) gain = 128 0.01 0.1 % gain = 1 0.2 ppm/ c gain drift gain = 128 2.5 ppm/ c internal oscillator, f data = 10sps 100 110 db f in = 50hz or 60hz, 1hz normal-mode rejection (4) external oscillator, f data = 10sps 120 130 db f in = 50hz or 60hz, 1hz at dc, gain = 1, v = 1v 95 110 db common-mode rejection at dc, gain = 128, v = 0.1v 95 110 db input-referred noise see noise performance tables at dc, gain = 1, v = 1v 100 120 db power-supply rejection at dc, gain = 128, v = 0.1v 100 120 db voltage reference input voltage reference input (v ref ) v ref = vrefp ? vrefn 1.5 avdd avdd + 0.1v v negative reference input (vrefn) agnd ? 0.1 vrefp ? 1.5 v positive reference input (vrefp) vrefn + 1.5 avdd + 0.1 v voltage reference 10 na input current (1) fsr = full-scale range = v ref /gain. (2) offset calibration can minimize these errors to the level of noise at any temperature. (3) gain errors are calibrated at the factory (avdd = +5v, all gains, t a = +25 c). (4) specification is assured by the combination of design and final production test. copyright ? 2005 ? 2008, texas instruments incorporated 3 product folder link(s): ads1232 ads1234 www.ti.com
ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 electrical characteristics (continued) all specifications at t a = ? 40 c to +105 c, avdd = dvdd = vrefp = +5v, and vrefn = agnd, unless otherwise noted. ads1232, ads1234 parameter conditions min typ max unit digital logic levels v ih 0.7 dvdd dvdd + 0.1 v v il dgnd 0.2 dvdd v v oh i oh = 1ma dvdd ? 0.4 v v ol i ol = 1ma 0.2 dvdd v input leakage 0 < v in < dvdd 10 m a external clock input frequency 0.2 4.9152 8 mhz (f clkin ) serial clock input frequency (f sclk ) 5 mhz power supply power-supply voltage 2.7 5.3 v (avdd, dvdd) normal mode, avdd = 3v, 600 1300 m a gain = 1, 2 normal mode, avdd = 3v, 1350 2500 m a gain = 64, 128 normal mode, avdd = 5v, 650 1300 m a analog supply current gain = 1, 2 normal mode, avdd = 5v, 1350 2500 m a gain = 64, 128 standby mode 0.1 1 m a power-down 0.1 1 a normal mode, dvdd = 3v, 60 95 a gain = 1, 2 normal mode, dvdd = 3v, 75 120 a gain = 64, 128 normal mode, dvdd = 5v, 95 130 a gain = 1, 2 digital supply current normal mode, dvdd = 5v, 75 120 a gain = 64, 128 standby mode, sclk = high, dvdd = 3v 45 80 a standby mode, sclk = high, dvdd = 5v 65 80 m a power-down 0.2 1.3 a normal mode, avdd = dvdd = 3v, 2 4.2 mw gain = 1, 2 normal mode, avdd = dvdd = 5v, 3.7 7.2 mw gain = 1, 2 power dissipation, total normal mode, avdd = dvdd = 3v, 4.3 7.9 mw gain = 64, 128 normal mode, avdd = dvdd = 5v, 7.1 13.1 mw gain = 64, 128 standby mode, avdd = dvdd = 5v 0.3 0.4 mw 4 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 www.ti.com
noise performance ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 the ads1232/4 offer outstanding noise performance that can be optimized for a given full-scale range using the on-chip programmable gain amplifier. table 1 through table 4 summarize the typical noise performance with inputs shorted externally for different gains, data rates, and voltage reference values. the rms and peak-to-peak noise are referred to the input. the effective number of bits (enob) is defined as: enob = ln (fsr/rms noise)/ln(2) the noise-free bits are defined as: noise-free bits = ln (fsr/peak-to-peak noise)/ln(2) where fsr (full-scale range) = v ref /gain table 1. avdd = 5v, v ref = 5v, data rate = 10sps gain rms noise peak-to-peak noise (1) enob (rms) noise-free bits 1 420nv 1.79v 23.5 21.4 2 270nv 900nv 23.1 21.4 64 19nv 125nv 22.0 19.2 128 17nv 110nv 21.1 18.4 (1) peak-to-peak noise data are based on direct measurement. table 2. avdd = 5v, v ref = 5v, data rate = 80sps gain rms noise peak-to-peak noise (1) enob (rms) noise-free bits 1 1.36v 8.3v 21.8 19.2 2 850nv 5.5v 21.5 18.8 64 48nv 307nv 20.6 18 128 44nv 247nv 19.7 17.2 (1) peak-to-peak noise data are based on direct measurement. table 3. avdd = 3v, v ref = 3v, data rate = 10sps gain rms noise peak-to-peak noise (1) enob (rms) noise-free bits 1 450nv 2.8v 22.6 20 2 325nv 1.8v 22.1 19.7 64 20nv 130nv 21.2 18.5 128 18nv 115nv 20.3 17.6 (1) peak-to-peak noise data are based on direct measurement. table 4. avdd = 3v, v ref = 3v, data rate = 80sps gain rms noise peak-to-peak noise (1) enob (rms) noise-free bits 1 2.2v 12v 20.4 17.9 2 1.2v 6.8v 20.2 17.8 64 54nv 340nv 19.7 17.1 128 48nv 254nv 18.9 16.5 (1) peak-to-peak noise data are based on direct measurement of 1024 samples. copyright ? 2005 ? 2008, texas instruments incorporated 5 product folder link(s): ads1232 ads1234 www.ti.com
pin configuration ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 6 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 www.ti.com dvdd dgnd clkin/xtal1 xtal2 dgnd dgnd a1 a0 cap cap ainp1 ainn1 ainp3 ainn3 drdy/dout sclk pdwn speed gain1 gain0 avdd agnd refp refn ainp2 ainn2 ainp4 ainn4 12 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ads1234 dvdd dgnd clkin/xtal1 xtal2 dgnd dgnd temp a0 cap cap ainp1 ainn1 drdy/dout sclk pdwn speed gain1 gain0 avdd agnd refp refn ainp2 ainn2 12 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 ads1232
ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 pin descriptions terminal analog/digital name ads1232 ads1234 input/output description dvdd 1 1 digital digital power supply: 2.7v to 5.3v dgnd 2 2 digital digital ground clkin/ external clock input: typically 4.9152mhz. tie low to activate internal oscillator. can also use 3 3 digital/digital input xtal1 external crystal across clkin/xtal1 and xtal2 pins. see text for more details. xtal2 4 4 digital external crystal connection dgnd 5 5 digital digital ground dgnd 6 6 digital digital ground temp 7 ? digital input onboard temperature diode enable input mux select input pin (msb) input mux select input pin (lsb): a1 a0 channel a1 ? 7 digital input 0 0 ain1 a0 8 8 0 1 ain2 1 0 ain3 1 1 ain4 cap 9 9 analog gain amp bypass capacitor connection cap 10 10 analog gain amp bypass capacitor connection ainp1 11 11 analog input positive analog input channel 1 ainn1 12 12 analog input negative analog input channel 1 ainp3 ? 13 analog input positive analog input channel 3 ainn3 ? 14 analog input negative analog input channel 3 ainn4 ? 15 analog input negative analog input channel 4 ainp4 ? 16 analog input positive analog input channel 4 ainn2 13 17 analog input negative analog input channel 2 ainp2 14 18 analog input positive analog input channel 2 refn 15 19 analog input negative reference input refp 16 20 analog input positive reference input agnd 17 21 analog analog ground avdd 18 22 analog analog power supply, 2.7v to 5.3v gain select gain1 gain0 gain 0 0 1 gain0 19 23 digital input gain1 20 24 0 1 2 1 0 64 1 1 128 data rate select: speed data rate speed 21 25 digital input 0 10sps 1 80sps pdwn 22 26 digital input power-down: holding this pin low powers down the entire converter and resets the adc. serial clock: clock out data on the rising edge. also used to initiate offset calibration and sleep sclk 23 27 digital input modes. see text for more details. dual-purpose output: drdy/ 24 28 digital output data ready: indicates valid data by going low. dout data output: outputs data, msb first, on the first rising edge of sclk. copyright ? 2005 ? 2008, texas instruments incorporated 7 product folder link(s): ads1232 ads1234 www.ti.com
typical characteristics ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 at t a = +25 c, avdd = dvdd = vrefp = 5v, and vrefn = agnd, unless otherwise noted. noise plot noise plot figure 1. figure 2. noise histogram noise histogram figure 3. figure 4. noise plot noise plot figure 5. figure 6. 8 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 time (reading number) output code (lsb) 70 50 30 10 - 10 - 30 - 50 - 70 200 400 600 800 1000 0 pga = 128 data rate = 80sps output code (lsb) occurrence 300 250 200 150 100 50 0 - 4 - 2 0 2 4 pga = 1 data rate = 10sps time (reading number) output code(lsb) 22.5 17.5 12.5 7.5 2.5 - 2.5 - 7.5 - 12.5 - 17.5 - 22.5 200 400 600 800 1000 0 pga = 1 data rate = 80sps time (reading number) output code (lsb) 65 4 3 2 1 - 1 - 2 - 3 - 4 - 5 - 6 200 400 600 800 1000 0 pga = 1 data rate = 10sps output code (lsb) occurrence 100 90 80 70 60 50 40 30 20 10 0 - 16 16 8 0 - 8 pga = 128 data rate = 10sps time (reading number) output code (lsb) 25 20 15 10 50 - 5 - 10 - 15 - 20 - 25 200 400 600 800 1000 0 pga = 128 data rate = 10sps www.ti.com
ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 typical characteristics (continued) at t a = +25 c, avdd = dvdd = vrefp = 5v, and vrefn = agnd, unless otherwise noted. noise histogram noise histogram figure 7. figure 8. offset drift ( ? 40 c to +25 c) offset drift (+25 c to +105 c) figure 9. figure 10. gain drift ( ? 40 c to +25 c) gain drift (+25 c to +105 c) figure 11. figure 12. copyright ? 2005 ? 2008, texas instruments incorporated 9 product folder link(s): ads1232 ads1234 output code (lsb) occurance 50 45 40 35 30 25 20 15 10 50 - 40 - 20 0 20 40 pga = 128 data rate = 80sps offset drift (nv/ c) - 500 - 400 - 300 - 200 - 100 0 100 200 300 400 500 3530 25 20 15 10 50 counts pga = 1data rate = 10sps 90 samples from 3 lots gain drift (ppm/ c) - 1.0 - 0.9 - 0.8 - 0.7 - 0.6 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0 0.10.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2018 16 14 12 10 86 4 2 0 counts pga = 1data rate = 10sps 90 samples from 3 lots output code (lsb) occurance 180 160 140 120 100 80 60 40 20 0 - 12 - 6 12 6 0 pga = 1 data rate = 80sps offset drift (nv/ c) - 600 - 500 - 400 - 300 - 200 - 100 0 100 200 300 400 500 600 3530 25 20 15 10 50 counts pga = 1data rate = 10sps 90 samples from 3 lots www.ti.com gain drift (ppm/ c) - 1.2 - 1.1 - 1.0 - 0.9 - 0.8 - 0.7 - 0.6 - 0.5 - 0.4 - 0.3 - 0.2 - 0.1 0 0.10.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1816 14 12 10 86 4 2 0 counts pga = 1data rate = 10sps 90 samples from 3 lots
ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 typical characteristics (continued) at t a = +25 c, avdd = dvdd = vrefp = 5v, and vrefn = agnd, unless otherwise noted. offset drift ( ? 40 c to +25 c) offset drift (+25 c to +105 c) figure 13. figure 14. gain drift ( ? 40 c to +25 c) gain drift (+25 c to +105 c) figure 15. figure 16. offset vs temperature gain error vs temperature figure 17. figure 18. 10 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 offset drift (nv/ c) - 50 - 40 - 30 - 20 - 10 0 10 20 30 40 50 3025 20 15 10 50 counts pga = 128 data rate = 10sps 90 samples from 3 lots offset drift (nv/ c) - 30 - 25 - 20 - 15 - 10 - 5 0 5 10 15 20 25 30 2018 16 14 12 10 86 4 2 0 counts pga = 128 data rate = 10sps 90 samples from 3 lots temperature ( c) offset (nv) 1000 500 0 - 500 - 1000 110 - 50 - 30 - 10 10 30 50 70 90 pga = 128 data rate = 10sps gain drift (ppm/ c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2520 15 10 50 counts pga = 128 data rate = 10sps 90 samples from 3 lots www.ti.com gain drift (ppm/ c) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2018 16 14 12 10 86 4 2 0 counts pga = 128 data rate = 10sps 90 samples from 3 lots temperature ( c) gain error (%) 0.04 0.03 0.02 0.01 0 - 0.01 - 0.02 110 - 50 - 30 - 10 10 30 50 70 90 pga = 128 data rate = 10sps
ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 typical characteristics (continued) at t a = +25 c, avdd = dvdd = vrefp = 5v, and vrefn = agnd, unless otherwise noted. noise vs input signal noise vs input signal figure 19. figure 20. integral nonlinearity integral nonlinearity vs input signal vs input signal figure 21. figure 22. analog current digital current vs temperature vs temperature figure 23. figure 24. copyright ? 2005 ? 2008, texas instruments incorporated 11 product folder link(s): ads1232 ads1234 v in (v) inl (ppm of fsr) inl ( m v) 54 3 2 1 0 - 1 - 2 - 3 - 4 - 5 25 20 15 10 5 0 - 5 - 10 - 15 - 20 - 25 2.5 - 2.5 - 2.0 - 1.5 - 0.5 - 1.0 1.0 0 0.5 1.5 2.0 pga = 1 temperature ( c) digital current ( m a) 120 100 80 60 40 20 0 110 - 50 - 30 - 10 10 30 50 70 90 normal mode, pga = 64, 128 normal mode, pga = 1, 2 sleep mode, all pgas v in (v) rms noise (nv) 1000 900 800 700 600 500 400 300 200 100 0 2.5 - 2.5 - 2.0 - 1.5 - 0.5 - 1.0 1.0 0 0.5 1.5 2.0 pga = 1 data rate = 10sps v in (mv) rms noise (nv) 50 45 40 35 30 25 20 15 10 50 19 - 19 - 14.25 - 9.5 - 4.75 4.75 0 9.5 14.25 pga = 128 data rate = 10sps temperature ( c) analog current ( m a) 2000 1600 1200 800 400 0 110 - 50 - 30 - 10 10 30 50 70 90 normal mode, pga = 64, 128 normal mode, pga = 1, 2 v in (mv) inl (ppmof fsr) inl (nv) 10 86 4 2 0 - 2 - 4 - 6 - 8 - 10 390.625 312.5 234.375 156.25 78.125 0 - 78.125 - 156.25 - 234.375 - 312.5 - 390.625 19 - 19 - 14.25 - 9.5 - 4.75 4.75 0 9.5 14.25 pga = 128 www.ti.com
ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 typical characteristics (continued) at t a = +25 c, avdd = dvdd = vrefp = 5v, and vrefn = agnd, unless otherwise noted. data rate vs temperature figure 25. 12 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 temperature ( c) data rate (sps) 10.06 10.01 9.96 9.91 9.86 110 - 50 - 30 - 10 10 30 50 70 90 speed = low clkin/xtal1 = low (internal oscillator) www.ti.com
overview temperature sensor (ads1232 only) analog inputs (ainpx, ainnx) ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 the ads1232 and ads1234 are highly integrated, on-chip diodes provide temperature-sensing 24-bit adcs that include an input multiplexer, capability. by setting the temp pin high, the selected low-noise pga, third-order delta-sigma ( ) analog inputs are disconnected and the inputs to the modulator, and fourth-order digital filter. with adc are connected to the anodes of two diodes input-referred rms noise down to 17nv, the scaled to 1x and 80x in current and size, as shown in ads1232/4 are ideally suited for measuring the very figure 26 . by measuring the difference in voltage of low signals produced by bridge sensors in these diodes, temperature changes can be inferred applications such as weigh scales, strain gauges, and from a baseline temperature. typically, the difference pressure sensors. in diode voltage is 111.7mv at 25 c with a temperature coefficient of 379 m v/ c. with pga = 1 clocking can be supplied by an external oscillator, an and 2, the difference voltage output from the pga will external crystal, or by a precision internal oscillator. be 111.7mv and 223.4mv, respectively. with pga = data can be output at 10sps for excellent 50hz and 64 and 128, it is impossible to use the temperature 60hz rejection, or at 80sps when higher speeds are sensor function. a similar structure is used in the needed. the ads1232/4 are easy to configure, and msc1210 for temperature measurement. for more all digital control is accomplished through dedicated information, see ti application report sbaa100 , pins; there are no registers to program. a simple using the msc121x as a high-precision intelligent two-wire serial interface retrieves the data. temperature sensor, available for download at www.ti.com . the input signal to be measured is applied to the input pins ainpx and ainnx. the positive internal input is generalized as ainp, and the negative internal input generalized as ainn. the signal is selected through the input mux, which is controlled by pins a0 and a1 (ads1234 only), as shown in table 5 . for the ads1232, the a1 pin is replaced by the temp pin to activate the onboard diodes (see the temperature sensor section for more details). the ads1232/4 accept differential input signals, but can also measure unipolar signals. when measuring unipolar (or single-ended signals) with respect to ground, connect the negative input (ainnx) to ground and connect the input signal to the positive input (ainpx). note that when the ads1232/4 are configured this way, only half of the converter full-scale range is used, since only positive digital output codes are produced. table 5. input channel selection with a0 and a1 (ads1234 only) mux pins selected analog inputs a1 a0 positive input negative input 0 0 ainp1 ainn1 0 1 ainp2 ainn2 1 0 ainp3 ainn3 1 1 ainp4 ainn3 figure 26. measurement of the temperature sensor in the input multiplexer copyright ? 2005 ? 2008, texas instruments incorporated 13 product folder link(s): ads1232 ads1234 www.ti.com a0 a1 ainp ainp1 ainn1 ainp2 ainn2 ainp3 ainn3 ainp4 ainn4 10i 1i 1x 8x ainn ads1232 only avdd ads1234 only
bypass capacitor low-noise pga voltage reference inputs ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 by applying a 0.1f external capacitor (c ext ) across the ads1232/4 features a low-drift, low-noise pga two capacitor pins and the combination of the internal that provides a complete front-end solution for bridge 2k ? resistor r int on-chip, a low-pass filter (with a sensors. a simplified diagram of the pga is shown in corner frequency of 720hz) is created to bandlimit the figure 27 . it consists of two chopper-stabilized signal path prior to the modulator input. this low-pass amplifiers (a1 and a2) and three accurately-matched filter serves two purposes. first, the input signal is resistors (r 1 , r f1 , and r f2 ), which construct a bandlimited to prevent aliasing as well as to filter out differential front-end stage with a gain of 64, followed the high-frequency noise. second, it attenuates the by gain stage a3. the pga inputs are equipped with chopping residue from the pga (for gains of 64 and an emi filter, as shown in figure 27 . the cut-off 128 only) to improve temperature drift performance. it frequency of the emi filter is 19.6mhz. if the pga is is not required to use high quality capacitors (such as set to 1 or 2, the gain-of-64 stage is bypassed and ceramic or tantalum capacitors) for a general shut down to save power. with the combination of application. however, high quality capacitors such as both gain stages, the pga can be set to 64 or 128. poly are recommended for high linearity applications. the pga of the ads1232/4 can be set to 1, 2, 64, or 128 with pins gain1 (msb) and gain0 (lsb). by using avdd as the reference input, the bipolar input ranges from 2.5v to 19.5mv, while the unipolar (refp, refn) ranges from 2.5v to 19.5mv. when the pga is set to the voltage reference used by the modulator is 1 or 2, the absolute inputs can go rail-to-rail without generated from the voltage difference between refp significant performance degradation. however, the and refn: v ref = refp ? refn. the reference inputs of the ads1232/4 are protected with internal inputs use a structure similar to that of the analog diodes connected to the power-supply rails. these inputs. in order to increase the reference input diodes will clamp the applied signal to prevent it from impedance, a switching buffer circuitry is used to damaging the input circuitry. on the other hand, when reduce the input equivalent capacitance. the the pga is set to 64 or 128, the operating input range reference drift and noise impact adc performance. in is limited to (agnd + 1.5v) to (avdd ? 1.5v), in order to achieve best results, pay close attention to order to prevent saturating the differential front-end the reference noise and drift specifications. a circuitry and degrading performance. simplified diagram of the circuitry on the reference inputs is shown in figure 28 . the switches and capacitors can be modeled with an effective impedance of: where: f mod = modulator sampling frequency (76.8khz) c buf = input capacitance of the buffer for the ads1232/4: figure 27. simplified diagram of the pga 14 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 z eff 1 2 f mod c buf r int r int r f1 r 1 r f2 adc a3 gain of 1 or 2 cap ainp ainn cap a2 a1 450 w 18pf 450 w 18pf www.ti.com
clock sources ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 figure 29. equivalent circuitry of the clock source when the clock source is a crystal, simply connect the 4.9152mhz crystal across the clkin/xtal1 and xtal2 pins. table 6 shows the recommended part numbers. due to the low-power design of the parallel resonant driver circuitry onboard, both the figure 28. simplified reference input circuitry clkin/xtal1 and xtal2 pins are only for use with external crystals; they should not be used as clock output drivers for external circuitry. no external esd diodes protect the reference inputs. to prevent capacitors are used with the crystal; it is these diodes from turning on, make sure the voltages recommended to place the crystal close to the part in on the reference pins do not go below gnd by more order to reduce board stray capacitance for both the than 100mv, and likewise, do not exceed avdd by clkin/xtal1 and xtal2 pins and to insure proper 100mv: operation. gnd ? 100mv < (refp or refn) < avdd + 100mv table 6. recommended crystals manufacturer frequency part number the ads1232/4 can use an external clock source, ecs 4.9152mhz ecs-49-20-1 external crystal, or internal oscillator to accommodate ecs 4.9152mhz ecs-49-20-4 a wide variety of applications. figure 29 shows the equivalent circuitry of the clock source. the clk_detect block determines whether the crystal an external oscillator may be used by driving the oscillator/external clock signal is applied to the clkin/xtal1 pin directly. the electrical clkin/xtal1 pin so that the internal oscillator is characteristics table shows the allowable frequency bypassed or activated. when the clkin/xtal1 pin range. frequency is above ~200khz, the clk_detect output goes low and shuts down the internal oscillator. when the xin pin frequency is below ~200khz, the clk_detect output goes high and activates the internal oscillator. it is highly recommended to hard-wire the clkin/xtal1 pin to ground when the internal oscillator is chosen. copyright ? 2005 ? 2008, texas instruments incorporated 15 product folder link(s): ads1232 ads1234 clk_detect internal oscillator mux to adc s s0 s1 en crystal oscillator clkin/xtal1 xtal2 avdd (1) f mod = 76.8khz z eff = 500m w (1) vrefp vrefn avdd esd protection c buf z eff 1 (2)(76.8khz)(13ff) 500m www.ti.com
frequency response ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 figure 31 (b) shows the zoom in plot for both 50hz and 60hz notches with the speed pin tied low the ads1232/4 use a sinc 4 digital filter with the (10sps data rate). with only a 3% variation of the frequency response (f clk = 4.9152mhz) shown in internal oscillator, over 100db of normal-mode figure 30 . the frequency response repeats at rejection is achieved. multiples of the modulator sampling frequency of 76.8khz. the overall response is that of a low-pass filter with a ? 3db cutoff frequency of 3.32hz with the speed pin tied low (10sps data rate) and 11.64hz with the speed pin tied high (80sps data rate). figure 30. frequency response to help see the response at lower frequencies, figure 31 (a) illustrates the response out to 100hz, when the data rate = 10sps. notice that signals at multiples of 10hz are rejected, and therefore simultaneous rejection of 50hz and 60hz is achieved. the benefit of using a sinc 4 filter is that every figure 31. frequency response out to 100hz frequency notch has four zeros on the same location. this response, combined with the low drift internal oscillator, provides an excellent normal-mode the ads1232/4 data rate and frequency response rejection of line-cycle interference. scale directly with clock frequency. for example, if f clk increases from 4.9152mhz to 6.144mhz when the speed pin is tied high, the data rate increases from 80sps to 100sps, while notches also increase from 80hz to 100hz. note that this is only possible when the external clock source is applied. 16 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 frequency (khz) gain (db) 0 - 20 - 40 - 60 - 80 - 100 - 120 - 140 - 160 - 180 - 200 38.4 76.8 0 f clk = 4.9152mhz www.ti.com frequency (hz) gain (db) 0 - 50 - 100 - 150 0 10 20 30 40 50 60 70 80 90 100 (a) frequency (hz) (b) gain (db) - 50 - 100 - 150 49 48 46 47 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 data rate = 10sps data rate = 10sps
settling time ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 switching input channels. another example would be toggling the temp pin, which switches the internal after changing the input multiplexer, the first data are ainp, ainn signals to connect to either the external fully settled. in both the ads1232/4, the digital filter is ainpx, ainnx pins or to the temp diode (see allowed to settle after toggling either the a1 or a0 pin. figure 26 ). toggling any of these digital pins will hold the drdy/dout line high until the digital filter is fully note that when settling data, five readings may be settled. for example, if a0 changes from low to high, required. if the change in input occurs in the middle selecting a different input channel, drdy/dout of the first conversion, four more full conversions of immediately goes high, and drdy/dout goes low the fully-settled input are required to get fully-settled when fully-settled data are ready for retrieval. there data. discard the first four readings because they is no need to discard any data. figure 32 shows the contain only partially-settled data.figure 33 illustrates timing of the drdy/dout line as the input the settling time for the ads1232/4 in continuous multiplexer changes. conversion mode. in certain instances, large and/or abrupt changes in input will require four data cycles to settle. one example of such a change would be an external multiplexer in front of the ads1232/4, which can cause large changes in input voltage simply by figure 32. example of settling time after changing the input multiplexer symbol description (1) min max units t s setup time for changing the a1 or a0 pins 40 50 m s speed = 1 51 51 ms settling time ( drdy/dout t 1 held high) speed = 0 401 401 ms (1) values given for f clk = 4.9152mhz. for different f clk frequencies, scale proportional to clk period. expect a 3% variation when an internal oscillator is used. figure 33. settling time in continuous conversion mode copyright ? 2005 ? 2008, texas instruments incorporated 17 product folder link(s): ads1232 ads1234 toggled temp pin or abrupt change in external v in v in drdy /dout start ofconversion. 1st conversion;includes unsettled v . in 2nd conversion; v settled, but in digital filterunsettled. 3rd conversion; v settled, but in digital filterunsettled. 4th conversion; v settled, but in digital filterunsettled. 5th conversion; v and digital in filter bothsettled. conversion time a1 or a0 t 1 drdy /dout t s www.ti.com
data rate data ready/data output ( drdy/dout) serial clock input (sclk) data format ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 the ads1232/4 data rate is set by the speed pin, this digital output pin serves two purposes. first, it as shown in table 7 . when speed is low, the data indicates when new data are ready by going low. rate is nominally 10sps. this data rate provides the afterwards, on the first rising edge of sclk, the lowest noise, and also has excellent rejection of both drdy/dout pin changes function and begins 50hz and 60hz line-cycle interference. for outputting the conversion data, most significant bit applications requiring fast data rates, setting speed (msb) first. data are shifted out on each subsequent high selects a data rate of nominally 80sps. sclk rising edge. after all 24 bits have been retrieved, the pin can be forced high with an table 7. data rate settings additional sclk. it will then stay high until new data are ready. this configuration is useful when polling data rate on the status of drdy/dout to determine when to speed internal oscillator external begin data retrieval. pin or 4.9152mhz crystal oscillator 0 10sps f clkin / 491,520 1 80sps f clkin / 61,440 this digital input shifts serial data out with each rising edge. this input has built-in hysteresis, but care should still be taken to ensure a clean signal. glitches or slow-rising signals can cause unwanted additional the ads1232/4 output 24 bits of data in binary two ? s shifting. for this reason, it is best to make sure the complement format. the least significant bit (lsb) rise-and-fall times of sclk are less than 50ns. has a weight of 0.5v ref /(2 23 ? 1). the positive full-scale input produces an output code of 7fffffh and the negative full-scale input produces an output code of 800000h. the output clips at these codes for signals exceeding full-scale. table 8 summarizes the ideal output codes for different input signals. table 8. ideal output code vs input signal (1) input signal v in (ainp ? ainn) ideal output code +0.5v ref /gain 7fffffh (+0.5v ref /gain)/(2 23 ? 1) 000001h 0 000000h ( ? 0.5v ref /gain)/(2 23 ? 1) ffffffh ? 0.5v ref /gain 800000h (1) excludes effects of noise, inl, offset, and gain errors. 18 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 www.ti.com
data retrieval ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 indicating that new data are being updated. to avoid having drdy/dout remain in the state of the last the ads1232/4 continuously convert the analog bit, the user can shift sclk to force drdy/dout input signal. to retrieve data, wait until drdy/dout high, as shown in figure 35 . this technique is useful goes low, as shown in figure 34 . after this occurs, when a host controlling the device is polling begin shifting out the data by applying sclks. data drdy/dout to determine when data are ready. are shifted out msb first. it is not required to shift out all 24 bits of data, but the data must be retrieved before new data are updated (within t 7 ) or else it will be overwritten. avoid data retrieval during the update period (t 6 ). drdy/dout remains at the state of the last bit shifted out until it is taken high (see t 6 ), figure 34. data retrieval timing symbol description min typ max units t 2 drdy/dout low to first sclk rising edge 0 ns t 3 sclk positive or negative pulse width 100 ns sclk rising edge to new data bit valid: propagation t 4 50 ns delay t 5 sclk rising edge to old data bit valid: hold time 0 ns t 6 (1) data updating: no readback allowed 39 m s speed = 1 12.5 ms t 7 (1) conversion time (1/data rate) speed = 0 100 ms (1) values given for f clk = 4.9152mhz. for different f clk frequencies, scale proportional to clk period. figure 35. data retrieval with drdy/dout forced high afterwards copyright ? 2005 ? 2008, texas instruments incorporated 19 product folder link(s): ads1232 ads1234 drdy/dout 23 22 21 1 24 0 lsb msb data data ready sclk t 2 t 7 t 3 t 3 t 6 new data ready t 4 t 5 23 1 24 25 22 21 0 data 25th sclk to force drdy/dout high data ready new data ready drdy/dout sclk www.ti.com
offset calibration ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 when the calibration is completed, drdy/dout goes low, indicating that new data are ready. the offset calibration can be initiated at any time to analog input pins are disconnected within the adc remove the ads1232/4 inherited offset error. to and the appropriate signal is applied internally to initiate offset calibration, apply at least two additional perform the calibration. the first conversion after a sclks after retrieving 24 bits of data. figure 36 calibration is fully settled and valid for use. the offset shows the timing pattern. the 25th sclk will send calibration takes exactly the same time as specified in drdy/dout high. the falling edge of the 26th sclk (t 8 ) right after the falling edge of the 26th sclk. will begin the calibration cycle. additional sclk pulses may be sent after the 26th sclk; however, activity on sclk should be minimized during offset calibration for best results. figure 36. offset-calibration timing symbol description min max units speed = 1 101.28 101.29 ms t 8 (1) first data ready after calibration speed = 0 801.02 801.03 ms (1) values given for f clk = 4.9152mhz. for different f clk frequencies, scale proportional to clk period. expect a 3% variation when an internal oscillator is used. 20 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 23 drdy/dout sclk 1 24 t 8 25 26 23 22 21 0 data ready after calibration calibration begins www.ti.com
standby mode ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 when t 10 has passed with sclk held high, standby mode will activate. drdy/dout stays high when standby mode dramatically reduces power standby mode begins. sclk must remain high to consumption by shutting down most of the circuitry. in stay in standby mode. to exit standby mode standby mode, the entire analog circuitry is powered (wakeup), set sclk low. the first data after exiting down and only the clock source circuitry is awake to standby mode is valid. reduce the wake-up time from the standby mode. to enter standby mode, simply hold sclk high after drdy/dout goes low; see figure 37 . standby mode can be initiated at any time during readback; it is not necessary to retrieve all 24 bits of data beforehand. figure 37. standby mode timing (can be used for single conversions) symbol description min max units speed = 1 0 12.44 ms sclk high after drdy/dout goes low t 9 (1) to activate standby mode speed = 0 0 99.94 ms speed = 1 12.46 ms t 10 (1) standby mode activation time speed = 0 99.96 ms speed = 1 52.51 52.51 ms t 11 (1) data ready after exiting standby mode speed = 0 401.8 401.8 ms (1) values given for f clk = 4.9152mhz. for different f clk frequencies, scale proportional to clk period. expect a 3% variation when an internal oscillator is used. copyright ? 2005 ? 2008, texas instruments incorporated 21 product folder link(s): ads1232 ads1234 drdy/dout 23 22 21 1 24 0 23 sclk standby mode start conversion data ready t 9 t 10 t 11 www.ti.com
standby mode with ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 to force an offset-calibration with standby mode, shift offset-calibration 25 sclks and take the sclk pin high to enter standby mode. offset-calibration then begins after offset-calibration can be set to run immediately after wake-up; see figure 38 for the appropriate timing. exiting standby mode. this is useful when the note the extra time needed after wake-up for ads1232/4 is put in standby mode for long periods calibration before data are ready. the first data after of time, and offset-calibration is desired afterwards to standby mode with offset-calibration is fully settled compensate for temperature or supply voltage and can be used right away. changes. figure 38. standby mode with offset-calibration timing (can be used for single conversions) symbol description min max units speed = 1 103 103 ms data ready after exiting standby mode t 12 (1) and calibration speed = 0 803 803 ms (1) values given for f clk = 4.9152mhz. for different f clk frequencies, scale proportional to clk period. expect a 3% variation when an internal oscillator is used. 22 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 standby mode begin calibration data ready after calibration t 10 t 12 drdy/dout 23 1 24 25 22 21 0 23 sclk www.ti.com
power-up sequence power-down mode ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 when powering up the ads1232/34, avdd and dvdd must be powered up before the pdwn pin goes high, as shown in figure 39 . if pdwn is not controlled by a microprocessor, a simple rc delay circuit must be implemented, as shown in figure 40 . figure 39. power-up timing sequence power-down mode shuts down the entire adc circuitry and reduces the total power consumption close to zero. to enter power-down mode, simply hold the pdwn pin low. power-down mode also resets the entire circuitry to free the adc circuitry from locking up to an unknown state. power-down mode can be initiated at any time during readback; it is not necessary to retrieve all 24 bits of data beforehand. figure 41 shows the wake-up timing from power-down mode. figure 40. rc delay circuit figure 41. wake-up timing from power-down mode symbol description typ units internal clock 7.95 m s t 13 wake-up time after power-down mode external clock 0.16 m s crystal oscillator (1) 5.6 ms t 14 (2) pdwn pulse width 26 (min) m s (1) no capacitors on clkin/xtal1 or xtal2 outputs. (2) value given for f clk = 4.9152mhz. for different f clk frequencies, the scale is proportional to the clk period except for a 3% variation when an internal oscillator is used. copyright ? 2005 ? 2008, texas instruments incorporated 23 product folder link(s): ads1232 ads1234 avdd dvdd pdwn 3 m 10 s data ready start conversion drdy/dout sclk clk soure wakeup power-down mode pdwn t 13 t 11 t 14 dvdd (1) connect toads1232/34 pin pdwn 1k w 2.2nf note: (1) avdd must be powered up at least 10 s before goes high. m pdwn www.ti.com
application examples weigh-scale system thermocouple ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 therefore: figure 42 shows a typical ads1232 hook-up as part with +5v supply voltage, 177,385 noise-free counts of a weigh-scale system. in this setup, the ads1232 can be expected from the ads1232/4 with the is configured to channel one input with a gain of 128 onboard pga set to 128. at a 10sps data rate. note that the internal oscillator is used by grounding the clkin/xtal1 pin. the user can also apply either a 4.9152mhz crystal across the clkin/xtal1 and xtal2 pins, or simply apply a see figure 43 for the ads1232 in a thermocouple clock to the clkin/xtal1 pin. for a typical 2mv/v application. in this example, a type k thermocouple is load cell, the maximum output signal is approximately used; the temperature range is from ? 260 c to 10mv for a single +5v excitation voltage. the +900 c when the gain is set to 64 to maximize the ads1232/4 can achieve 18.4 noise-free bits at full input range of the ads1232. r 1 and a 10sps when the pga = 128 (refer to table 1 ). with ref1004-2.5v are used to set the common-mode the extra software filtering/averaging (typically done voltage to 2.5v for ungrounded junction by a microprocessor), an extra bit can be expected. thermocouples. with a gain of 128, the ads1232 input has a typical noise of 17nv rms for extremely high-resolution applications. if either a wider temperature range application is where: required (up to +1350 c, for example), or a grounded junction thermocouple is used, pin 1 of the bit eff = effective noise-free bits (18.4 + 1 bit thermocouple can be grounded (see figure 44 ). from software filtering/averaging) when the gain is set to 2, the ads1232 input has a fs lc = full-scale output of the load cell (10mv) typical 500nv offset error and a noise level of fs ad = full-scale input of the ads1232/4 (39mv 270nv rms , which is good for all kinds of low-voltage when pga = 128) output sensors. note that to calculate the actual thermocouple temperature, the ads1232 internal temperature sensor can be accessed in order to measure the cold junction temperature along with the thermocouple reading. 24 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 noise?free counts 2 (18.4 1) 10mv 39mv 177, 385 www.ti.com noise?free counts 2 bit eff fs lc fs ad
ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 figure 42. weigh scale application figure 43. ungrounded junction thermocouple application copyright ? 2005 ? 2008, texas instruments incorporated 25 product folder link(s): ads1232 ads1234 ads1232 16 9 1011 12 14 13 15 2019 24 23 22 4 3 21 8 7 refpcap cap ainp1 ainn1 ainp2 ainn2 refn gain0 avdd dvdd agnd dgnd drdy/dout sclk pdwn xtal2 clkin/xtal1 speed a0 temp 0.1 f m 0.1 f m 5v 3v gain1 + - 17 2, 5, 6 18 1 msp430x4xx or other microprocessor vdd gnd gain = 128 ads1232 16 9 1011 12 14 13 15 2019 24 23 22 4 3 21 8 7 refpcap cap ainp1 ainn1 ainp2 ainn2 refn gain0 avdd dvdd agnd dgnd drdy/dout sclk pdwn xtal2 clkin/xtal1 speed a0 temp 0.1 f m 0.1 f m 5v 3v gain1 17 2, 5, 6 18 1 msp430x4xx or other microprocessor vdd gnd gain = 128 r 1 50k w ref1004- 2.5v 2 1 thermocouple type k www.ti.com
ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 figure 44. grounded junction thermocouple application 26 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 ads1232 16 9 1011 12 14 13 15 1920 24 23 22 4 3 21 8 7 refpcap cap ainp1 ainn1 ainp2 ainn2 refn gain1 avdd dvdd agnd dgnd drdy/dout sclk pdwn xtal2 clkin/xtal1 speed a0 temp 0.1 f m 0.1 f m 5v 3v gain0 17 2, 5, 6 18 1 msp430x4xx or other microprocessor vdd gnd gain = 2 r 1 50k w ref1004- 2.5v 2 1 thermocouple type k www.ti.com
rtds and thermistors ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 by using both differential channels of the ads1232, the temperature change in lead resistance, r l , can figure 45 shows a typical schematic for a style 2 be eliminated. this condition is accomplished by (three-wire) rtd application. r 1 and r 2 are used to using the following formula: excite the rtd as well as establish the common-mode voltage of the ads1232 pga. (ainp1 ? ainn1) ? 2(ainp2 ? ainn2). figure 45. style 2 (three-wire) rtd schematic copyright ? 2005 ? 2008, texas instruments incorporated 27 product folder link(s): ads1232 ads1234 ads1232 16 9 1014 11 13 12 15 2019 24 23 22 4 3 21 8 7 refpcap cap ainp2 ainp1 ainn2 ainn1 refn gain0 avdd dvdd agnd dgnd drdy/dout sclk pdwn xtal2 clkin/xtal1 speed a0 temp 0.1 f m 0.1 f m 5v 3v gain1 17 2, 5, 6 18 1 msp430x4xx or other microprocessor vdd gnd gain = 128 r 1 33k w r 2 33k w r l r l r l rtd note: r is lead resistance. l www.ti.com
summary of serial interface waveforms ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 figure 46. summary of serial interface waveforms 28 copyright ? 2005 ? 2008, texas instruments incorporated product folder link(s): ads1232 ads1234 drdy/dout sclk 23 22 21 0 msb lsb 1 24 drdy/dout sclk 23 22 21 0 1 24 25 drdy/dout sclk 23 22 21 0 1 24 25 26 calibration begins data ready after calibration drdy/dout sclk data ready start conversion standby mode 23 22 21 0 1 24 drdy/dout sclk 23 22 21 0 1 24 25 data ready after calibration calibration begins (a) data retrieval (b) data retrieval with drdy/dout forced high afterwards (c) offset?calibration timing (d) standby mode/single conversions (e) standby mode/single conversions with offset calibrati on standby mode www.ti.com
ads1232 ads1234 sbas350f ? june 2005 ? revised february 2008 revision history changes from revision e (october 2007) to revision f ............................................................................................... page changed avdd to deltav in common-mode rejection section in electrical characteristics table....................................... 3 changed avdd to deltav in power-supply rejection section in electrical characteristics table ......................................... 3 changes from revision d (september 2007) to revision e .......................................................................................... page corrected unit values in electrical characteristics table ........................................................................................................ 3 changes from revision c (june 2006) to revision d .................................................................................................... page deleted logic level v ih row for clkin/xtal test condition in electrical characteristics ..................................................... 3 added offset drift and gain drift histogram plots to typical characteristics (figure 9 to figure 16 ) ...................................... 9 changed difference voltage output for pga = 2 from 323.4mv to 223.4mv in temperature sensor section .................... 13 added text to voltage reference inputs section regarding reference and drift noise ......................................................... 14 changed z eff equation ........................................................................................................................................................ 15 changed figure 28 ............................................................................................................................................................. 15 changed figure 29 ............................................................................................................................................................. 15 deleted last sentence of clock sources section ................................................................................................................. 15 changed text in settling time section ................................................................................................................................. 17 changed figure 32 ............................................................................................................................................................. 17 changed figure 33 ............................................................................................................................................................. 17 deleted 2nd sentence of serial clock input section ............................................................................................................ 18 added power-up sequence section, with new text and two new figures (figure 39 and figure 40 ). ................................ 23 changed figure 42 ............................................................................................................................................................. 25 changed figure 43 ............................................................................................................................................................. 25 changed figure 44 ............................................................................................................................................................. 26 changed figure 45 ............................................................................................................................................................. 27 changes from revision b (september 2005) to revision c .......................................................................................... page deleted last row from absolute maximum ratings table. ...................................................................................................... 2 changed analog inputs section of electrical characteristics table ....................................................................................... 3 changed the typical value in last row of voltage reference input section of electrical characteristics table ...................... 3 added footnote 1 to table 1 , table 2 , table 3 , and table 4 . ................................................................................................ 5 changed fourth sentence in temperature sensor section of overview . ............................................................................. 13 added fifth and sixth sentences to temperature sensor section of overview . ................................................................... 13 added fourth and fifth sentences to low-noise pga section of overview . ......................................................................... 14 changed figure 27 . ............................................................................................................................................................. 14 changed t 11 to t 10 in third paragraph of standby mode section of overview . ..................................................................... 21 changed min and max variables of t 10 row in table below figure 37 . ................................................................................. 21 changed figure 41 . ............................................................................................................................................................. 23 added last row and second footnote to table below figure 41 ............................................................................................ 23 copyright ? 2005 ? 2008, texas instruments incorporated 29 product folder link(s): ads1232 ads1234 www.ti.com
package option addendum www.ti.com 21-may-2010 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) ads1232ipw active tssop pw 24 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads1232ipwg4 active tssop pw 24 60 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads1232ipwr active tssop pw 24 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ads1232ipwrg4 active tssop pw 24 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ADS1234IPW active tssop pw 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ADS1234IPWg4 active tssop pw 28 50 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ADS1234IPWr active tssop pw 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year ADS1234IPWrg4 active tssop pw 28 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature.
package option addendum www.ti.com 21-may-2010 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ads1232ipwr tssop pw 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 q1 ADS1234IPWr tssop pw 28 2000 330.0 16.4 6.9 10.2 1.8 12.0 16.0 q1 package materials information www.ti.com 11-mar-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ads1232ipwr tssop pw 24 2000 346.0 346.0 33.0 ADS1234IPWr tssop pw 28 2000 346.0 346.0 33.0 package materials information www.ti.com 11-mar-2008 pack materials-page 2

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti ? s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. ti products are not authorized for use in safety-critical applications (such as life support) where a failure of the ti product would reasonably be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing such use. buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of ti products in such safety-critical applications, notwithstanding any applications-related information or support that may be provided by ti. further, buyers must fully indemnify ti and its representatives against any damages arising out of the use of ti products in such safety-critical applications. ti products are neither designed nor intended for use in military/aerospace applications or environments unless the ti products are specifically designated by ti as military-grade or " enhanced plastic. " only products designated by ti as military-grade meet military specifications. buyers acknowledge and agree that any such use of ti products which ti has not designated as military-grade is solely at the buyer ' s risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti products are neither designed nor intended for use in automotive applications or environments unless the specific ti products are designated by ti as compliant with iso/ts 16949 requirements. buyers acknowledge and agree that, if they use any non-designated products in automotive applications, ti will not be responsible for any failure to meet such requirements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications audio www.ti.com/audio communications and telecom www.ti.com/communications amplifiers amplifier.ti.com computers and peripherals www.ti.com/computers data converters dataconverter.ti.com consumer electronics www.ti.com/consumer-apps dlp ? products www.dlp.com energy and lighting www.ti.com/energy dsp dsp.ti.com industrial www.ti.com/industrial clocks and timers www.ti.com/clocks medical www.ti.com/medical interface interface.ti.com security www.ti.com/security logic logic.ti.com space, avionics and defense www.ti.com/space-avionics-defense power mgmt power.ti.com transportation and www.ti.com/automotive automotive microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com wireless www.ti.com/wireless-apps rf/if and zigbee ? solutions www.ti.com/lprf ti e2e community home page e2e.ti.com mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2011, texas instruments incorporated

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